`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:13:45 06/30/2015
// Design Name:   Etapa1
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/TrabajoFinalArquitectura/trunk/Final-Mips/Etapa1Test.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Etapa1
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Etapa1Test;

	// Inputs
	reg PCSrc;
	reg clk;
	reg reset;
	reg [31:0] BranchData;

	// Outputs
	wire [31:0] Instruccion;
	wire [31:0] E1Adder;

	// Instantiate the Unit Under Test (UUT)
	Etapa1 uut (
		.PCSrc(PCSrc), 
		.clk(clk), 
		.reset(reset), 
		.BranchData(BranchData), 
		.Instruccion(Instruccion), 
		.E1Adder(E1Adder)
	);

	initial begin
		// Initialize Inputs
		PCSrc = 0;
		clk = 0;
		reset = 0;
		BranchData = 0;

		// Wait 100 ns for global reset to finish
		#100;
      reset = 1;
		#1;
		reset = 0;
		#50;
		BranchData = 32'h 00000004;
		PCSrc = 1;
		#10;
		PCSrc = 0;

	end
always begin
#2; clk = ~clk;
end 
endmodule

